In order to meet higher and higher chip performance (speed) and density objectives, for the submicron era, increasing attention has been placed on multilevel-interconnect technology. The benefits of further reductions in device dimensions will not be fully realized unless the performance and density limitations of interconnects are also continually improved. Accordingly, the line spacing between metal interconnect lines has been continually deceased while the number of Multilevel Interconnect, MLI, layers have been continually increased. Unfortunately, this very necessary evolution in MLI development has not been easy. For example, there are yield and reliability issues that numerous investigators have attributed to a worsening degree of surface planarity (smoothness) that is aggravated by smaller line spacing and more MLI layers.
MLI structures are usually formed by stacking a number of patterned metal interconnect layers that are electrically isolated from one another by interlevel dielectric layers. The vertical step heights associated with each patterned metal layer create a rugged surface of spaced lines that is subsequently covered by a somewhat conformal dielectric layer, such as CVD or plasma TEOS. Due to the conformal nature of such dielectric processes, the surface of each dielectric layer tends to replicate the rugged topology of the underlying pattered metal layer. Consequently, each succeeding patterned metal layer needs to somehow be formed on a dielectric surface whose topology is increasingly more rugged than that of the previous underlying dielectric layer. This poses a limit on the number of patterned metal layers that one can stack before serious yield and reliability problems are encountered.
Yield problems can be encountered when the degree of planarity is not sufficient for the depth-of-field limitations associated with optical lithography exposure tools. For example, the resolution of sub-micron optical lithography will be degraded if the localized step heights on a chip surface are greater than 0.5 microns.
Reliability problems can be encountered when insufficient surface planarity leads to the formation of undesirable gaps, seams and voids in the interlevel dielectric layers. These problems can more readily occur when closely spaced metal lines are covered by a conformal insulating layer. For example, in the case of submicron line spacing, the adjacent side walls of the conformal insulating layer will be so much closer together than the side walls of the underlying metal lines that they can tend to almost touch or actually touch. Such close proximity of adjacent insulator side walls can lead to the formation of narrow gaps, seams and voids along their line of intersection. In turn, these gaps, seams and voids can become locations of chemical entrapment and eventual reliability problems.
Efforts to overcome some of the above problems associated with insufficient surface planarity have dealt with the need to improve the planarity of the metal layers and as well as that of the interlevel insulator layers. To date, more effort has been put into improving the planarity of the insulator layers. This has, for example, included: (1) Thermal flow of insulators (such as boron doped CVD oxides) for smoothing undesirably steep steps, (2) Growth of thicker than required insulator layers (thicker layers tend to be smoother), followed by an etch back process and (3) numerous ways of exploiting Spin On Glass, SOG, as a self planarizing insulator layer.
Spin On Glass, SOG, has many desirable attributes. It can be applied in a liquid state (spun on similar to photoresist), whereby it will automatically tend to fill all undesirable gaps and globally planarize an entire wafer as it naturally seeks its own level.
SOG materials are organic siloxanes or silicates mixed in alcohol-based solvents. After being spun on, a series of relatively low temperature (in the range of 150-400 C) baking and curing steps are used to drive off the solvent and then to convert the SOG to an inorganic silicon dioxide layer.
There have been numerous variations on the usage of SOG in the semiconductor industry, as a means of improving planarization during the formation of multilevel interconnect layers. In many cases SOG has been a useful means of achieving a planar surface. However, SOG also has its own problems. For example, poor adhesion to conventional CVD layers can lead to delamination problems and air bubbles can eventually lead to poorly formed via holes.
Regarding SOG, there is prior art which addresses the problems from both poor adhesion and air bubbles. For the case of undesired air bubbles, solutions have been published for minimizing their initial creation. However air bubbles in SOG do not seem to be completely preventable and once created they can be a serious problem, particularly in the vicinity of eventual via holes. Consequently, a solution is needed for minimizing the detrimental effects of some degree of unavoidable air bubbles in cured SOG layers. The present invention addresses that need.
U.S. Pat. No. 4,676,867, to Elkins, et. al., teaches a method of planarization, whereby a SOG layer is first applied over the surface of a conventional non-planar insulating layer (such as a doped CVD oxide) to provide a planarized surface. The cured SOG layer is then sacrificially etched back to partially expose the underlying insulator. This is purposely done to minimize SOG related problems, associated with adhesion and the etching of vias in SOG. Finally, an additional insulating layer (such as doped CVD oxide) is deposited which preserves planarity while increasing the overall thickness of the composite insulating layer to the desired value. However, during the SOG etch back step, the detrimental effects of the localized absence of SOG (due to air bubbles originally in the SOG layer, for example) could still present a problem.
U.S. Pat. No. 4,775,550, to Chu, et. al, teaches a method of planarization, similar to that of Elkins, et. al, above. Also similar to Elkins, et. al., the detrimental effects of the localized absence of SOG (due to air bubbles originally in the SOG layer) during the etch back step could still present a problem.
U.S. Pat. No. 5,554,567, to Wang, teaches a method to minimize the adhesion problems associated with SOG. The moisture level in the SOG is kept low by baking the SOG in a vacuum and then maintaining a vacuum while the SOG layer is then passivated by an overlying oxide layer (such as CVD oxide). This method is featured as a means of allowing a SOG layer to remain on a surface without having to perform the somewhat complicated etch back step in the above patents. However, it does not address the problems that could occur during the etching of via holes in SOG, as a result of air bubbles originally in the SOG layer.
U.S. Pat. No. 5,429,912, to Neoh, teaches a method that might, conceivably, be used to minimize air bubbles in SOG layers. Bubble free liquid is drawn from the bottom of a well during the spin on process of liquids, such as photoresist or developer. However, it does not specifically address SOG or how to minimize the detrimental effects of air bubbles, in SOG layers, after they have been created.